The present invention relates in general to communication circuits and components and support structures therefor, and is particularly directed to a new and improved multi-layer printed circuit architecture for high power RF devices that provides low-inductance and low thermal resistance interconnections to a relatively thick, thermal dissipation, ground plane support substrate.
Associated with continuing improvements in component micro-miniaturization, integration density and operational frequencies of signal processing and communication circuits, especially those employed in high frequency and high power RF applications, are packaging design and fabrication techniques that will facilitate the practical implementation of an integrated circuit architecture. As diagrammatically illustrated in FIG. 1, a typical printed circuit board structure, such as that employed for RF applications, is configured as a multi-layered laminate of dielectric layers (D1, D2, D3) interleaved with patterned conductive layers (L1, L2, L3), which respectively provide RF signaling and shielding, digital and analog control, and DC power functions.
This multi-layer laminate is supported atop a conductive (e.g., copper) ground plane substrate L4, that may serve as or be attached to a thermal dissipation medium, serving as a ground plane and mechanically stable support. Integrated circuit components and devices 10 may be surface-mounted to signal traces of the topside patterned conductor layer L1 formed on the relatively thick dielectric layer D1. The multi-layer laminate structure contains a distribution of conductively plated through-holes or vias (one of which is shown at 20), which provide xe2x80x98verticalxe2x80x99 or xe2x80x98through-the-stackxe2x80x99 interconnections among the various conductive layers of the laminated structure.
As shown in the interconnect schematic diagram of FIG. 2, such plated through-holes typically include the following: 1) through-hole interconnects 21 between the (RF signaling) conductive layer L1 and the (analog and digital signaling) layer L3; 2) through-hole interconnects 22 between (microstrip ground/RF shielding) layer L2 and the underlying ground plane and thermal dissipation support plate L4; and 3) through-hole interconnects 23 among the RF signaling layer L1, the microstrip ground layer L2 and the ground plane and thermal dissipation support plate L4.
In order to ensure proper operation of the composite circuit architecture, it is essential to minimize the reactance (parasitic capacitance, and inductance in particular) of interconnects. This mandates the use of shorter sections of conductive material, particularly at higher RF frequencies. Since the effective length of a section of interconnect includes both the vertical plated through-hole dimension and the horizontal dimension of a patterned conductive layer Li to which it is joined, a very efficacious technique to minimize grounding lead inductance is to fabricate such leads as a large number of closely spaced plated ground interconnect vias 22, that extend between the RF ground/shielding layer L2 and the bottom ground plate L4.
Unfortunately, this gives rise to a significant fabrication issuexe2x80x94ensuring that the plated ground vias 22 between the bottom layer L4 and RF ground/shield layer L2 do not extend all the way through the topside dielectric layer D1. If they did, the vias 22 would intersect the RF signal trace layer L1, and thereby short the RF signaling layer L1 to ground during a solder reflow step customarily used in the fabrication process. The basic problem is the substantial thickness of the copper substrate L4 upon which the interleaved dielectric and conductive layer laminate is mounted. In particular, providing the ground interconnects 22 requires the formation of conductive through holes through the stack between the RF shielding layer L2 and the ground plane layer L4.
One way to form the RF shield to ground vias 22 would be to drill holes from the bottom surface of the layer L4 up into the laminate, so as to intersect the RF shield layer L2. However, this approach demands a very exact (and therefore prohibitively expensive) vertical drilling depth through the dielectricxe2x80x94patterned conductor stack. This is especially true, if ground plane layer L4 has substantial thickness. The hole depths would have to be sufficient to intersect the target RF shield layer L2, but not puncture the topside dielectric layer D1. It may be noted that the problem cannot be avoided by simply increasing the thickness of the dielectric layer D1 (in order to increase the tolerance of the drill depth), since the characteristics of the dielectric layers (particularly those of the topside dielectric layer D1), including thickness and dielectric properties, must be tailored for proper circuit operation.
In accordance with the present invention, the above-described problems are effectively obviated by a new and improved multi-layer printed circuit architecture and fabrication process therefor, that facilitates forming a large number of closely spaced plated vias between a robust underlying ground plane support pallet and the RF shielding layer, in a manner that minimizes interconnect inductance, while at the same time preventing unwanted shorting of the RF signal trace layer to ground, during solder reflow for connection to xe2x80x98wide leadxe2x80x99 power devices.
By xe2x80x98wide leadxe2x80x99 is meant an interconnect medium having a dimension equal to or greater than one-twentieth of a wavelength of propagation within the dielectric material of the RF transmission line. The invention successfully addresses the issue of inductance in the ground return path of the high power device to be mounted in a device well. The sensitivity of the path between the RF shielding layer and the base of the device (which is attached to the underlying ground plane pallet) varies according to the input and output impedances of the device. For large power transistors, these impedances are very low, and the circuit is very sensitive to stray inductance.
As will be described, the multilayer printed circuit structure of the invention includes an interleaved laminate of patterned dielectric layers and patterned conductive layers. The conductive layers are used for RF signaling, RF microstrip shielding/ground, digital and analog control signal leads, and DC power. A vertical interconnect between the RF signaling layer and the control/DC conductive layer is provided by way of a plated bore that intersects material of each of these conductive layers. The RF shielding layer is patterned adjacent to the bore, so as to be laterally offset from bore and thereby prevent conductive material plated in the bore from electrically bridging the RF shielding layer.
A vertical interconnect that joins the RF signaling layer, the RF microstrip shielding layer and the underlying ground plane support pallet is realized by forming a plated bore completely through the laminate structure from the RF signaling layer down through the bottom dielectric layer and into or through the conductive pallet. The support pallet preferably comprises a relatively thick metallic substrate, that is patterned to provide recesses of appropriate depth that conform with each of device capture slots and bores in the laminate structure. Although this bore intersects each of the RF signaling layer and the RF microstrip layer, the DC/control layer is patterned so that the plated bore is laterally offset from it, to prevent the plated bore from contacting the DC/control layer.
In the course of forming a vertical interconnect that electrically joins the RF microstrip shielding layer with the underlying ground plane support pallet, a further bore is drilled completely through the laminate structure from the RF signaling layer down to and at least partially through the ground plane pallet. The further bore intersects each of the RF signaling layer and the microstrip shielding layer; however, the DC/control layer is patterned so as to be laterally offset from the further bore, to prevent conductive material plated in the bore from contacting the DC/control layer.
The bores used for ground plane interconnections are preferably formed through the overall laminate structure (including the pallet) after the conductorxe2x80x94dielectric laminate structure has been bonded to the pallet. The bores are then plated to interconnect the RF signalling layer to the bottom of each bore. Although this operation provides the intended interconnects for the RF signaling layer, it results in an unwanted shorting of the RF signaling layer to the vertical interconnect between the RF shield layer and the support pallet.
Pursuant to the invention, this problem is obviated by counter-drilling the plated bore used for the vertical interconnect between the RF shield layer and the ground plane pallet with an oversized drill, to form an oversized counterbore that extends to a prescribed depth from the RF signaling layer into the topside dielectric layer. Because the counter-drilling of this bore is from the top surface of the laminate and directly into the relatively thicker topside dielectric layer, precise control of the depth of the counterbore is readily achieved. In addition, the radius of the counter-drill is sufficiently larger than the radius of the bore per se, so that the circular perimeter of the counterbore overlaps and removes a prescribed portion of the conductive material plated in the bore.
The upper portions of the bores are then filled with electrically insulating (e.g., epoxy, glass, or other suitable insulating material) plugs. Because the counter-drilled bore no longer has plated material intersecting the RF signaling layer, its non-conductive plug provides an insulating barrier between the RF signaling layer and the plated conductor remaining in the bore. The conductive material remaining in the bore beneath the plug still provides the intended interconnect between the RF shielding layer and the ground plane pallet.
This insulator-filled counterbore structure allows a large number of such bores to be placed immediately adjacent to well regions where high power devices, such as RF power transistors and the like, are installed, so as to provide low inductance electrical and thermal interconnects between the RF ground, common terminals of such devices, and the ground plane/heat sink pallet, without the danger of being shorted to the topside RF signaling layer, during solder reflow of interconnect leads for the topside RF signaling layer and the well-installed device.